Over the past decades CMOS technology has been continuously scaling and resulted in sustained improvement in transistor speeds. However, achieving higher DC open-loop gain from the op-amps became challenging. Also, the transistor threshold voltages did not decrease at the same rate as the supply voltage. This thesis work presents a detailed comparative study on the DC open loop gain and voltage swing from two different CMOS topologies: A three-stage CMOS op-amp and a two-stage CMOS op amp with current buffer circuit. We have designed, simulated, and analyzed the two circuit topologies using industry standard Cadence OrCAD and Allegro SPB v17.4 software. The three-stage CMOS op-amp exhibited 156.55 dB, 428.67 MHz, and 670 as DC gain, GBW, and PM respectively. Whereas, the two-stage CMOS op-amp with current buffer circuit show 133.33 dB, 6.87 MHz, and 73.60 results of DC gain, GBW, and PM