The demand for maximum performance parameters, with some level of trade-o but not too much compromise between di erent parameters, from CMOS op-amp circuits in general and two stage CMOS op-amps in particular is driving researchers and designers to continuously work to achieve the best CMOS op-amp circuit design. With this in mind, the main task of the present research work is to construct (design) a two stage current bu er CMOS op-amp circuit which provides high DC open loop gain, Common Mode Rejection Ratio (CMRR), Slew Rate (SR) and low static power dissipation. The research involves three basic concepts, theoretical calculation, design, simulation, and then veri cation using CADENCE OrCAD PSPICE Design and Simulation software. Very high DC open loop gain, 141.236dB, greatly reduced power dissipation, 0.051mW, large SR (30V= s) and 36V= s and a CMRR of 66.058dB achieved from our work could make the design appropriate candidate for portable and DC-operated devices, such as medical devices, mobile phones, etc., that require very stable and free of noise (interference-free) operations.