Design and Simulation of A Fully Differential Cmos Op Amp

Andargie, Adelegn

dc.contributor.author	Andargie, Adelegn
dc.date.accessioned	2024-11-16T08:22:13Z
dc.date.available	2024-11-16T08:22:13Z
dc.date.issued	2024-10
dc.identifier.uri	http://ir.bdu.edu.et/handle/123456789/16160
dc.description.abstract	The need to design and manufacture CMOS ampliﬁers to maintain acceptable level of performances at low voltages is immensely important. This research work emphasizes on investigating the CMRR, slew rate, and DC gain of the fully diﬀerential CMOS op-amp using ORCAD PSPICE software. In this research work, the fully diﬀerential CMOS op-amp circuit operates at 3.3V power supply using 0.35 m CMOS technology. We have achieved a CMRR of 126.149dB, a DC open loop gain of 126.141dB, and the rising and falling slew rates were +17.76V/ s and -29.3V/ s respectively. The design was found to dissipate very small power ( 0.03685mW).	en_US
dc.language.iso	en_US	en_US
dc.subject	Physics	en_US
dc.title	Design and Simulation of A Fully Differential Cmos Op Amp	en_US
dc.type	Thesis	en_US