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| dc.contributor.author | Yewulsew, Manale | |
| dc.date.accessioned | 2024-05-20T08:03:24Z | |
| dc.date.available | 2024-05-20T08:03:24Z | |
| dc.date.issued | 2023-06 | |
| dc.identifier.uri | http://ir.bdu.edu.et/handle/123456789/15802 | |
| dc.description.abstract | Complementary Metal-Oxide Semiconductor (CMOS) technology becomes important in Radio Frequency (RF) communication systems, which include a transceiver (transmitter and receiver). In particular, in Wireless Sensor Network (WSN), transceiver is one of the most crucial and also the most power-hungry blocks. RF Integrated Circuit (RFIC) designers face challenges to design devices having Low power consumption, low cost of implementation, high level of integration, and high performance with lower power resources. The advancement of CMOS technologies has great advantages for RFIC designers to minimize challenges they face in the designs. This thesis presents Design of Low Power Wireless RF Receiver for WSN. The receiver operates at 900MHz [Industrial, Scientific, and Medical (ISM) band] and it is implemented in 90nm CMOS technology. The receiver has the following blocks: Low Noise Amplifier (LNA) for input matching and reducing input referred noise, Frequency Multiplication Mixer to be clocked from a lower frequency Local Oscillator (LO) operating at 300MHz (LO can be implemented using vertical delay cells to reduce power consumption), filter to provide selectivity for the signal of interest and to limit the noise, and Trans-impedance Amplifier (TIA) to convert current signal to voltage signal. By using current mode circuits and high selectivity filtering, we can improve linearity of the receiver. With such RF receiver architecture and implementation in mind, two of the most crucial blocks, namely LNA and TIA are designed at transistor-level within the scope of this thesis work. In a high-performance radio receiver, the LNA is the first circuit, and its noise performance dominates the entire receiver. Depending upon the gadget wherein they’re used, LNAs are designed in keeping with numerous topologies and structures. In this thesis, Capacitor Cross Coupled Differential Common Gate topology (CCC-DCG) is implemented. The other block is TIA, which is a current to voltage converter. Both blocks (LNTA and TIA) are designed at transistor-level on 90nm CMOS. The receiver conversion gain is above 40 dB and using advanced technology node helps to reduce the total power consumption (hence battery life) and area (hence cost). Key Words: CMOS, ISM band, Receiver, RF, WSN | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | Electrical and Computer Engineering | en_US |
| dc.title | Design of Highly Linear Low Power Wireless RF Receiver for Wireless Sensor Networks | en_US |
| dc.type | Thesis | en_US |
