Current Buffer Technique for a Two Stage Cmos Op Amp Design

Gizatu Mihiretie

dc.contributor.author	Gizatu Mihiretie
dc.date.accessioned	2023-03-23T07:34:53Z
dc.date.available	2023-03-23T07:34:53Z
dc.date.issued	2022-12
dc.identifier.uri	http://ir.bdu.edu.et/handle/123456789/15188
dc.description.abstract	The main task of this research is to study the current buffer technique for the two stage CMOS operational amplifier design. It involves three basic concepts, theoretical calculation, design, simulation, and verification using CADENCE Allegro SPB and OrCAD Capture software, which is based on analog and digital electronic devices and advanced integrated circuit design fundamentals. Our work on the two stage CMOS op amp circuit using the current buffer technique tried and achieved an increased DC open loop gain with a reduced power consumption. The two stage CMOS op amp design was operated at ± 3.5V power supply using 0.35µ m CMOS technology and was found to exhibit a CMRR of 131.806dB, SR of 50V/µs and -25V/µs, wide UGB of 50.362MHz, and a DC open loop gain of 131.806dB, which could be tailored for for medical device applications. Key Words: Two stage CMOS Op Amp, DC gain PD and CADENCE OrCAD PSPICE.	en_US
dc.language.iso	en_US	en_US
dc.subject	Physics	en_US
dc.title	Current Buffer Technique for a Two Stage Cmos Op Amp Design	en_US
dc.type	Thesis	en_US