Due to the problem of power dissipation, the demand for low power devices is increasing at a faster rate due to wider implementation of smaller-sized, portable, and hand held devices in the telecommunication and entertainment industries. This research study emphasizes on the design and analysis of the parameters of the two stage CMOS op amp with current buffer compensation method. We have designed a high gain and low power CMOS op amp, which operates at 3.0V power supply using 0.3 micron CMOS technology. The simulations were done using OrCAD PSPICE software and achieved an open loop gain of 131.34dB, UGB of 5.2657MHz and PM of 62.936 0 using a capacitive load of 5pF. The CMOS op amp also has a rising and falling slew rate SR(+) = 20V/µs and SR(-) = -25.439V/µs. The ICMR is -2.348V to 2.966V and CMRR is 83.985dB. The design was found to dissipate very small power P d = 0.156mW. Key words: Two-stage op amp, CMOS op-amp with Current Buffer, DC Open loop gain, slew rate, ORCAD PSPICE.