The main objective of this research is to design and simulate single ended two stage CMOS op amp by using OrCAD PSPICE design and simulation software, based on analog and digital electronic devices and advanced integrated circuit design fundamentals. Designers are continuously working toward trades-off solutions between DC open loop gain, input/output voltage swings, speed, power dissipation and gain bandwidth. The two stage CMOS op amp circuit proposed in this research tries to increase the DC open loop gain, phase margin, and reduce power dissipation. The two stage CMOS op amp was analyzed by considering the effects of aspect ratios on the characteristics of the design parameters such as, nodal voltage, node current, PD ICMR, voltage swing, SR, DC open loop gain, UGB, and CMRR when operating at ± 1.8V power supply using 1.0µ m CMOS technology. The designed two stages CMOS op amp was found to exhibit a DC open loop gain of 128.802dB, UGB of 2.1711MHz, SR of -40.0V/µs ; 40.05V/µs, and CMRR of 128.802dB, PD of 0.0457mW, ICMR of 2.837V. Key Words: Two stage CMOS Op Amp, SR, DC open loop gain, ICMR, CMRR, OrCAD PSPICE.