LOW VOLTAGE CMOS OP AMP DIFFERENTIAL INPUT/DIFFERENTIAL OUTPUT

Tigabu, Wuletaw

dc.contributor.author	Tigabu, Wuletaw
dc.date.accessioned	2019-09-23T04:35:26Z
dc.date.available	2019-09-23T04:35:26Z
dc.date.issued	2019-09-23
dc.identifier.uri	http://hdl.handle.net/123456789/9726
dc.description.abstract	Abstract Low voltage and low power operational ampliﬁer design has become an increasingly interesting subject as many applications switch to portable battery powered operations. The need for design techniques to allow ampliﬁers to maintain an acceptable level of performance when the supply voltages decreased is immense. This research work emphasizes on the study of the properties of the diﬀerential input/diﬀerential output CMOS ampliﬁer with low voltage. A method described in this thesis is to design a two stage fully diﬀerential CMOS op-amp and analyze the eﬀect of aspect ratios on the characteristics of the design parameters namely, nodal analysis (node voltage, node current, PD), DC sweep (ICMR), transient analysis (voltage swing, SR), and AC sweep (Open Loop Gain, UGB, CMRR) which operates at ± 2.5V power supply using 0.2µm CMOS technology. The design has been simulated with ORCAD Pspice soft ware. The op amp is designed to exhibit an open loop gain of 152.154dB (40,522,851.68 = 10 ), a unity gain band width of 4.8097MHz, output voltage swing of V is 2.0024V, CMRR of 152.165dB, the raising and failing slew rate of 12V/µs, -11.02V/µs, respectively. The design was found to dissipate very small power (≤ 0.333mW). The phase diﬀerence was 126.864 0 outpeaktopeak . Design has been carried out in mentor graph tools. Key words: CMOS, two-stage diﬀerential input/diﬀerential output op-amp, low voltage, slew rate, DC gain and ORCAD PSPICE. 7.6077	en_US
dc.language.iso	en_US	en_US
dc.subject	Physics	en_US
dc.title	LOW VOLTAGE CMOS OP AMP DIFFERENTIAL INPUT/DIFFERENTIAL OUTPUT	en_US
dc.type	Thesis	en_US