Mechanisms to Increase the Slew Rate and Open Loop Gain of a Two Stage Cmos Op Amp

Mahliet, Tesfa

dc.contributor.author	Mahliet, Tesfa
dc.date.accessioned	2026-08-21T05:38:05Z
dc.date.available	2026-08-21T05:38:05Z
dc.date.issued	2026-06-29
dc.identifier.uri	http://ir.bdu.edu.et/handle/123456789/17053
dc.description.abstract	The demand for low power, low voltage devices is increasing at a faster rate as a result of wider implementation of smaller-sized, portable, and hand held devices in the telecommunication and entertainment industries. This research study focuses on the mechanism to increase the slew rate and DC open loop gain of the two stage CMOS op-amp. We have designed the two stage CMOS op-amp, which operates at 2.0V power supply using 0.5 m CMOS technologies. The simulations were done using OrCAD PSPICE software and we have found that the design has high slew rate: -68.11V s, 72.06V s and high DC open loop gain of 95.29dB, widest UGB and PM of 11.24MHz and 84.62o, respectively. Thus, this design will be of highly capable candidate for portable and hand-held CMOS op amp devices.	en_US
dc.language.iso	en_US	en_US
dc.subject	Physics	en_US
dc.title	Mechanisms to Increase the Slew Rate and Open Loop Gain of a Two Stage Cmos Op Amp	en_US
dc.type	Thesis	en_US