Design of a High Slew Rate and High Open Loop Gain Two Stage Cmos Op Amp

Abayneh, Zewadie

dc.contributor.author	Abayneh, Zewadie
dc.date.accessioned	2024-11-16T11:42:34Z
dc.date.available	2024-11-16T11:42:34Z
dc.date.issued	2024-10
dc.identifier.uri	http://ir.bdu.edu.et/handle/123456789/16171
dc.description.abstract	Due to the problem associated with device power dissipation, the demand for low power devices is increasing at a faster rate as a result of wider implementation of smaller-sized, portable, and hand held devices in the telecommunication and entertainment industries. This research study is a comparative study which emphasizes on the design and analysis of the parameters of two stage CMOS op-amp technologies in order to get high slew rate and DC open loop gain. We have designed and compared some of the important performance parameters of the two stage CMOS op-amp, which operates at 2.0V power supply using L = 0.5 m CMOS technologies. The simulations were done using OrCAD PSPICE software and we have found that the design high slew rate: -61.98V s, 67.98V s and high DC open loop gain of 95.287dB, widest UGB and PM of 11.4233MHz and 84.7437 , respectively. Thus, this design will be of highly capable candidate for portable and hand-held CMOS op amp devices. o	en_US
dc.language.iso	en_US	en_US
dc.subject	Physics	en_US
dc.title	Design of a High Slew Rate and High Open Loop Gain Two Stage Cmos Op Amp	en_US
dc.type	Thesis	en_US