The Effect of Load Capacitances on the Icmr And Dc Gain of Differential Input/Output Cmos Op-Amp

Kindie, Yeshiwas

dc.contributor.author	Kindie, Yeshiwas
dc.date.accessioned	2024-03-28T06:17:51Z
dc.date.available	2024-03-28T06:17:51Z
dc.date.issued	2023-06
dc.identifier.uri	http://ir.bdu.edu.et/handle/123456789/15748
dc.description.abstract	Due to the problem associated with device power dissipation, the demand for high DC open loop gain, and wide input common mode range of voltage. CMOS circuit device is increasing at a faster rate because of a wider implementation of smaller sized, portable, and hand held devices in the telecommunication and entertainment industries. In this thesis work, the di erential input/di erential output CMOS op-amp circuit has been designed and simulations were carried out to investigate the e ect of load capacitance DC open loop gain and ICMR. We have designed four di erent di erential input/di erential output CMOS op-amp circuits with C = 1pF; 2pF; 5pF and 10pF and compared some of the important performance parameters: DC open loop gain and ICMR (also, power dissipation and UGB), which operates at 2.5V power supply using with 0.2 m CMOS technologies. The simulations were done using OrCAD PSPICE software and we have found that the design with C L = 2pF has the highest DC open loop gain of 140dB, ICMR of -1.862V to 2.477V, UGB of 6.45MHz and minimum PD of 0.0341mW. respectively. Thus, larger values of load capacitance were found to decrease the DC open loop gain and some what the ICMR. L	en_US
dc.language.iso	en_US	en_US
dc.subject	Physics	en_US
dc.title	The Effect of Load Capacitances on the Icmr And Dc Gain of Differential Input/Output Cmos Op-Amp	en_US
dc.type	Thesis	en_US