SINGLE ENDED OUTPUT FOLDED CASCODE CMOS OPERATIONAL AMPLIFIER

YOHANNES ADDIS

dc.contributor.author	YOHANNES ADDIS
dc.date.accessioned	2021-02-24T10:58:34Z
dc.date.available	2021-02-24T10:58:34Z
dc.date.issued	2021-02-24
dc.identifier.uri	http://ir.bdu.edu.et/handle/123456789/11955
dc.description.abstract	The main task of this research is to design and simulate single-ended output folded cascode CMOS op amp by using OrCAD PSPICE Design and Simulation software based on analog and digital electronic devices and advanced integrated circuit design fundamentals. It involves three basic concepts, theoretical calculation, design, and simulation verification using OrCAD PSPICE software. The single-ended output folded cascode CMOS op amp was analyzed by considering the effects of aspect ratios on the characteristics of the design parameters such as, nodal analysis, DC sweep (node voltage, node current, PD), transient analysis (Input/Output Voltage Swing and Slew Rate) and AC Sweep (DC open loop gain, UGB, CMRR). The simulation results show that the design of the single-ended output folded cascode CMOS op amp has an open loop gain of 54.013dB, CMRR of 52.138dB, unity gain frequency of 14.032MHz, slew rate of 2.081V/µs, and ICMR of 516.000mV to 517.000V. A 5pF load capacitor is applied in performing a stable phase margin of 67.3360 . It operates at 2.5V power supply with a very low power dissipation of 0.035379mW Key Words: Folded cascode, PD, ICMR, Open loop gain, CMRR and OrCAD PSPICE.	en_US
dc.language.iso	en	en_US
dc.subject	Physics	en_US
dc.title	SINGLE ENDED OUTPUT FOLDED CASCODE CMOS OPERATIONAL AMPLIFIER	en_US
dc.type	Thesis	en_US