Low power operational amplifier with a rail-to-rail voltage design has become an increasingly interesting subject as many applications switch to portable battery powered operations. The need for design techniques to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense. One of the most important features in low voltage amplifier designs is ensuring that the amplifier maintains constant behavior in the presence of rail-to-rail input common mode variations while providing a rail-to-rail output to maximize signal-to-noise ratio. In this thesis work, rail-to-rail differential CMOS operational amplifier has been designed using 2µm CMOS technology with the help of PSPICE deign and simulation software. The simulation results show the designed of rail-to-rail differential CMOS op-amp has an open loop gain of 16.242dB, CMRR of 16.242dB, unity gain frequency of 560.246KHz, slew rate of ±5V/µs, and ICMR of -2.1424V to 1.8400V. A 50pF load capacitor is applied in performing a stable phase margin of 81.0350 . It operates at ±2.2V power supply with a very low power dissipation of 1.9324mW. Key Words: CMOS, Op-Amp, Transconductance, Rail-to-Rail, PSPICE Software.