Due to the problem associated with device power dissipation, the demand for low power devices is increasing at a faster rate as a result of wider implementation of smaller-sized, portable, and hand held devices in the telecommunication and enter- tainment industries.In this thesis work, two stage CMOS op-amp technologies has been designed and simulations in order to achieve high open loop gain and low power dissipation. We have designed and compared some of the important performance parameters of the two stage CMOS op-amp, which operates at 1.8V power supply using L= 0.2 m, 0.25 m, 0.3 m, and 0.35 m CMOS technologies. The simulations were done using OrCAD PSPICE software and we have found that the design with L = 0.2 m has the most optimal performance parameters with highest open loop gain of 144.66dB, widest ICMR of -1.774V to 1.154V, lowest PD of 0.019mW, moderate UGB and PM of 4.1MHz and 104.3o, respectively. Thus, this design will be highly capable candidate for portable and hand-held CMOS op-amp devices. Key Words: Two stage CMOS Op Amp, PD, ICMR, Open Loop Gain, PM, UGB,